Non-volatile memory devices may be classified into two basic types, floating gate type non-volatile memory devices, and charge-trap type non-volatile memory devices. A floating gate type non-volatile memory device stores electrical charges in a floating gate as free carriers, and a charge-trap type non-volatile memory device stores electrical charges in spatially-isolated traps within a charge-trap layer.
A floating gate type non-volatile memory device may provide lower integration (device density) because of a height of a floating gate. Moreover, as a floating gate type non-volatile memory semiconductor device is more highly integrated, distances between floating gates are shortened, and defective operations may occur due to an interference effect between the floating gates. Also, since a floating gate type non-volatile memory device stores electrical charges as free carriers, a floating gate type non-volatile memory device may require a thick tunnel insulating layer as compared to a charge-trap type non-volatile memory device. Accordingly, a floating gate type non-volatile memory device may consume more power than a charge-trap type non-volatile memory device.
An example of a conventional charge-trap type non-volatile memory device is a silicon-oxide-nitride-oxide-silicon (SONOS) memory device. A SONOS memory device uses polysilicon as a gate electrode, silicon oxide as a tunnel-insulating layer and as a blocking insulating layer, and silicon nitride as a charge-trap layer between two insulating layers.
Electrical charges that are once trapped in the silicon nitride layer providing charge-trapping may not significantly move horizontally. Accordingly, at least two adjacent memory cell transistors may share a charge-trap layer in a conventional SONOS memory device. Recent research has revealed, however, that some charge in the silicon nitride layer may move horizontally. Horizontal movement of electrical charge may cause loss of charge, thereby changing a threshold voltage of a memory cell transistor.
In a conventional SONOS memory device, when an erase operation is performed by discharging electrical charge trapped in the charge-trap layer to a semiconductor substrate, a negative voltage may be applied to word lines. Here, since both of the blocking insulating layer and the tunnel-insulating layer are formed of silicon oxide, dielectric constants of the two layers may be the same, and thus almost the same electric field may be provided at the two insulating layers, causing back tunneling. For this reason, charge trapped in the charge-trap layer may not be completely discharged, and may stay in the charge-trap layer. To reduce occurrence of this defective erase operation, the blocking insulating layer may be made of a high-dielectric material having a greater dielectric constant than that of silicon oxide, and the gate electrode may be made of a material having a higher work function than that of polysilicon. When the blocking insulating layer formed of the high dielectric material is etched, however, the blocking insulating layer may be damaged by a plasma generated during dry-etching, which may generate defects on a sidewall of the blocking insulating layer. Problems such as breakdown voltage drop may thus result, thereby reducing reliability of the charge-trap type non-volatile memory device.